FIG. 1 shows one example of a comparator CHF according to the prior art.
The comparator CHF comprises an input interface comprising the input terminals E1 and Eref and an output interface comprising an output terminal S.
The comparator additionally comprises an amplifier comprising a preamplifier device 1 and a gain amplifier denoted by reference number 2.
The preamplifier device 1 comprises inputs that are connected to the terminals E1 and Eref and outputs S11 and S12 that are connected to inputs E21 and E22 of the gain amplifier device 2, respectively.
The comparator CHF comprises a latch stage 3 comprising input terminals E31 and E32 that are connected to outputs S21 and S22, respectively, of the gain amplifier device 2. The latch stage 3 comprises an output terminal S.
The preamplifier device 1 additionally comprises a control input Ec that is connected to the terminal S.
The terminal E1 is intended to receive a signal s1 and the terminal Eref is intended to receive a reference signal s2, and the terminal S is intended to receive a signal s. The operating frequency of the comparator CHF is, for example, of the order of 200 MHz corresponding to a first duration of propagation Tp of 5 ns for the signals s1 and s2 from the inputs E1 and Eref to the output S of the comparator CHF.
The preamplifier device 1 comprises operational amplifiers operating in their linear region, close to their equilibrium point, and a hysteresis device controlled by the input Ec.
The outputs S11 and S12 deliver signals s11 and s12.
The gain amplifier device 2 generally comprises multiple amplification stages linked in cascade fashion, each stage comprising multiple operational amplifiers operating in their linear region. The operational amplifiers are generally connected in the inverting configuration known to a person skilled in the art.
The outputs S21 and S22 deliver signals s21 and s22.
The latch stage 3 generally comprises a flip-flop, a first input of which is linked to the input E31 and a second input of which is linked to the input E32. The signals s21 and s22 are applied to the inputs E31 and E32.
FIG. 2 illustrates one example of a latch stage 3 according to the prior art.
It comprises a flip-flop device 10 comprising a first steering input S1 corresponding to a first output Q1 and a second steering input R1 corresponding to a second output Qb1.
The flip-flop device 10 comprises a flip-flop, for example an RS flip-flop.
When the steering input S1 is activated, the output Q1 is a logical “1” and the output Qb1 is equal to “0”. When the steering input R1 is activated, the output Qb1 is a logical “1” and the output Q1 is equal to “0”.
When the inputs S1 and R1 are activated simultaneously, the outputs Q1 and Qb1 retain their state prior to the change of state of the inputs S1 and R1.
The input S1 of the flip-flop device 10 is linked to the terminal E31, the input R1 of the flip-flop device 10 is linked to the output of a NAND logic gate 6 including two inputs, a first input of which is linked to the terminal E31 and the second input of which is linked to the terminal E32. The output Qb1 of the device 10 is linked to the input of an inverter logic gate 7. The output of the logic gate 7 is linked to the output terminal S.
Depending on the relative value of the signals s1 and s2, the flip-flop delivers a signal s that is equal to a logical “1” to the output terminal S if s1 is higher than s2, otherwise the signal s is equal to a logical “0”.
The latch stage 3 compares the signals s21 and S22 and converts the signal resulting from the comparison of the signals s21 and S22 to a digital signal s at the terminal S.
In order to react rapidly to small variations in the input signal s1, the high-frequency comparator CHF exhibits high gain and wide bandwidth.
The signals s1 and s2 are for example amplified by the devices 1 and 2 with a gain of around 100 dB.
This value of the output S is transmitted to the input Ec.
Since the devices 1 and 2 operate close to their equilibrium point, a very small variation in one of their inputs may cause the signal s to flip.
As such, noise in the comparator CHF may cause the output of the latch stage 3, and thus the logic state of the terminal of output S of the comparator CHF, to vary.
Since noise is by definition random, the signal s is made to oscillate, delivering a succession of logical 0s and 1s without the input signals s1 and s2 of the comparator CHF varying.
The hysteresis device incorporated in the preamplifier 1 suppresses the occurrence of the oscillations caused by noise by modifying the value of the signal s1 each time the signal s output by the comparator CHF changes state. It adds or subtracts an offset value Vdec to/from the signal s1 each time the signal s changes state. This offset value is added to s1 if the output signal s is equal to 1 or subtracted from s1 if the output signal s is equal to 0. This fixed value is known as a hysteresis value. This offset in the value of the signal s1 prevents the output S of the comparator from flipping upon each variation in the comparison signal that is less than or more than the predefined value Vdec.
However, when the oscillations resulting from noise are substantially of the same period, or of a period that is shorter than that of the first duration of propagation Tp of the signals through the comparator CHF, for example of the order of 5 ns, the signal s11 including the offset value does not have time to propagate through the comparator CHF. The output S of the comparator is then made to oscillate.
FIG. 3 illustrates the operation of the comparator CHF subject to noise on its input E1.
The signals output by the devices 1 and 2 exhibit a delay that is equal to the duration of propagation of the signals through the devices, for example the preamplifier device 1 has a duration of propagation tg.
The variations in the signal s with respect to the signal s1 output by the comparator CHF exhibit a delay that is equal to the first duration of propagation Tp. Consequently, the hysteresis value Vdec is applied to the signal s11 at the moment in time at which the signals s1 and s2 cross plus the first duration Tp. Noise occurs at time tB for a duration Tb that is shorter than the first duration of propagation Tp. Consequently, hysteresis is activated after the disturbance has passed through the comparator CHF. A variation in the signal s is observed for a duration Tb. Hysteresis has not made the comparator immune to noise.
Filtering devices, in particular digital filters placed at the output of the comparator, allow the oscillations to be filtered.
However, filtering devices require additional clocks of higher frequency than the operating frequency of the comparator in order to avoid the output of the comparator exhibiting latency, and additional circuits.
These additional elements lead to an additional power consumption of the order of twice the power consumption of the comparator CHF, and make the comparator more complex.